Recently, with development in the field of the information communication equipment, the processing ability required of the LSI is becoming higher, and correspondingly, the operating speed of transistors is increasing. Up to now, the device structure has to be miniaturized in order to cope with such increase in the operating speed of transistors. However, it is becoming difficult to reduce the gate length due to limitations imposed on the photolithographic technique, while it is becoming difficult to reduce the film thickness of the gate insulating film due to physical factors.
For this reason, there is a demand for techniques for achieving high performance of LSIs by routes other than device size miniaturization. Among such techniques, there is such a technique consisting in applying the stress to apply strain to the channel to improve the mobility (piezo-resistance effect). In a known manner, if a tensile (or compressive) stress is applied in a parallel (horizontal) direction to the channel to induce strain, the electron mobility is improved (or deteriorated), while the hole mobility is deteriorated (or improved). Several techniques for improving the performance of LSIs by taking advantage of this phenomenon have so far been disclosed (see for example Patent Documents 1 and 2).
In Patent Document 1, there is disclosed a technique in which a silicon nitride film is used as a stopper film at the time of opening a contact hole. This silicon nitride film is subjected to high tensile stress to induce strain to the channel to improve the electron mobility thereby improving the performance of the n-channel MISFET (abbreviated herein to nMISFET).
In Patent Document 2, there is disclosed a technique in which the nMISFET is covered with a silicon nitride film being under the tensile stress, and a p-channel MISFET (abbreviated herein to pMISFET) is covered with another silicon nitride film being under the compression stress, thereby to improve the mobility of both carriers to improve the performance of both the nMISFET and the pMISFET.    Patent Document 1: JP Patent Kokai Publication No. JP-P2002-198368A    Patent Document 2: JP Patent Kokai Publication No. JP-P2003-86708A    Non-Patent Document 1: “Journal Vacancy Science Technology (J. Vac. Sci. Technol.”, US, 1998, A16(4), p 2003    Non-Patent Document 2: “Journal Vacancy Science Technology (J. Vac. Sci. Technol.” US, 1999, A17(5), p 2612